1. Field of the Invention
The present invention relates generally to a testing apparatus for semiconductor devices, and more particularly, to an apparatus which is used to perform an alternating current (AC) test and a burn-in test on non-packaged or bare semiconductor chips.
2. Description of the Related Art
The semiconductor industry is now producing multi-chip modules (MCM) in which multiple semiconductor chips are mounted on a circuit board, rather than utilizing a single chip package. The multi-chip module (MCM) have several advantages including faster operating speeds, larger capacity, and higher integration densities.
Although these advantages are significant, the MCM suffers some drawbacks. As compared with the single chip package technique, the MCM has an increased integration scale, but the production yield is significantly decreased. Such a low yield means that an undesirably large quantity of material must be discarded or reworked, which is very expensive and labor intensive.
Therefore, it is important to identify known good die (KGD) to increase the production yield of the MCM. Known good die (KGD) are semiconductor chips which are not packaged but which have proven to be reliable after completing tests at the same level as the conventional package technique. The successful development of the MCM depends on the availability of the KGD.
Semiconductor chips are generally subjected to a series of test procedures in order to assure the reliability of the chips. One of these test procedures is an AC test in which all input and output terminals are connected to a test signal generating circuit to verify the transferring characteristics between the incoming and outgoing signals.
Another test is a burn-in test in which a given chip is overstressed, that is, the chip is subjected to higher than normal operating temperatures and voltages to verify its lifetime. These tests allow a manufacturer to identify defective chips and preclude potential failures which may occur after assembly or processing.
However, bare chips do not have external leads so it is difficult to electrically connect a non-packaged chip or a bare chip to the test signal generating circuit unless the chip is packaged. Thus, the tests are generally carried out by packaging the chip with external leads connected to chip pads, and connecting the external leads to a test socket, which is then mounted onto a test board. But, this test technique has disadvantages such as the cost involved in packaging a potentially inferior chip. Also, the tests are performed on one chip at a time, which limits the number of bare chips that may be tested in a given amount of time.
An apparent solution to these problems was proposed in U.S. Pat. No. 5,006,792, which provides a flip chip test socket adapter to perform the AC and burn-in tests with a bare chip, in which a plurality of solder bumps are formed on the bonding pads of the chip. As stated in the '792 patent, the flip chip is inserted into the test socket adapter and is subjected to the tests. The test socket adapter includes a substrate provided with cantilever beams to accommodate silicon substrates that are not perfectly flat or solder bumps that are not identical in size. The test socket adapter allows the bare chip to be tested prior to being packaged.
However, in this conventional technique, expensive chip test equipment must be provided so as to precisely form the solder bumps on the bonding pads of the chip due to a fine pitch between the bonding pads. Another problem is that the chip test is performed on only one chip at a time in order to assure the reliability. Thus, the cost for one validating a KGD is increased and the testing procedure is not advantageous for producing a large number of the KGDs. Furthermore, the chip must be individually handled during the test which makes it more difficult. Moreover, whenever the structure of the chip to be tested is changed, the structure of the above-described socket adapter must also be modified to correspond to different configurations of bonding pads.
Another technique for testing the bare chip is disclosed in U.S. Pat. No. 5,479,105 which provides a die testing apparatus including a lead frame which has bare chips mounted on die pads. The die pads are supported by tie bars and the leads are supported by an adhesion tape. The bare chips are connected to leads through wires. The lead frame is placed in a test socket which includes an under socket and an upper socket. The under socket has slot grooves and the upper socket, which is connected via a hinge with the under socket, has slot holes and test probes contacting the leads of the lead frame. The lead frame is fixed between the upper and under sockets by means of pins penetrating the slot holes and guiding holes located at a periphery of the lead frame, and then being inserted into the slot grooves. One side of the lead frame is fixed between the upper and under sockets by a clamp. The test socket, which has a plug portion with electrical contacts thereon, is located at an edge of the socket so that it can be plugged into a testing board.
Although this testing technique overcomes the problems of the above-described technique, it still suffers some drawbacks. First, since the plug portion of this test socket must be perpendicularly inserted into a test board, the lead frame having the bare chips connected to leads through the wires is oriented in an upright position. Accordingly, the wires are liable to break under harsh environments. Second, pins must be inserted through the slot holes, guiding holes and the slot grooves whenever the test socket is closed, which takes time and lowers productivity.